About VDP of msx1 & 2

Hi, two questions:

1) We all know that the msx1 is "powered" by the tms vdp series, later Yamaha develop a clone of this for msx2.

would be nice to know if, TMS had in it's price list
at the time of MSX1 / MSX2 VDP a more performant chip available, and if yes where i can find info about it?

This Wikipedia article summarizes the Texas Instruments and Yamaha followups nicely.

I know that Texas Instruments released a graphic processor around 1985/1986, the TMS34010, but I don't know if it shares some compatibilities with the MSX VDP. It should be interesting to check some infos about it.
Look here

Texas Instruments did move on to the 16/32 bit world quickly with highprice segment CPUs and GPUs, and left the homecomputing world early.

About the Interleaved question does anyone think it was possibile to gain cmd engine speed by using interleaved also in sc5/6?in screen 8 there are 2 pages available.

Page 0 uses VRAM addresses
$00000-$07FFF ,and
$10000-$17FFF

Page 1 uses VRAM addresses
$08000-$0FFFF ,and
$18000-$1FFFF

so if in page 0 of screen 8 you would put a dot at coordinate (0,0)
a byte needs to be written to VRAM address $00000
And if you would put a dot in page 0 at coordinate (1,0)
a byte needs to be written to VRAM address $10000

screen 5 has 4 pages available,
and they use these addresses:
page 0: $00000-$07FFF
page 1: $08000-$0FFFF
page 2: $10000-$17FFF
page 3: $18000-$FFFFF

So basically interlacing, the same way as in screen 8 would be possible if you would set your pages like this:

page 0: $00000-$03FFF and $10000-$13FFF
page 1: $04000-$07FFF and $14000-$17FFF
page 2: $08000-$0BFFF and $18000-$1BFFF
page 3: $0C000-$0FFFF and $1C000-$1FFFF

so to answer your question:
Sure the speed would increase IF interlacing would have been made possible in screen 5.

In screen 8 there are 2 pages available.

Page 0 uses VRAM addresses
$00000-$07FFF ,and
$10000-$17FFF

Page 1 uses VRAM addresses
$08000-$0FFFF ,and
$18000-$1FFFF

so if in page 0 of screen 8 you would put a dot at coordinate (0,0)
a byte needs to be written to VRAM address $00000
And if you would put a dot in page 0 at coordinate (1,0)
a byte needs to be written to VRAM address $10000
Ehm...

10 SCREEN8: CLS: VPOKE &H8000,255: A$=INPUT$(1)

shows a white dot at (0,128) on page 0, not a white dot at (0,0) on page 1...
I guess that you mean that if you putz around in the above address ranges in SCREEN 5, the putzing shows up in the mentioned pages in SCREEN 8, right?

(Or does BASIC mangle the address given to VPOKE?)
interlacing
Nope, interleaving. There's a difference

for the vdp user perspective in all modes vram appears as non interleaved...