MSX1 Memory Mapper | MSX Resource Center (Página 4/20)

Hero (534)

15-02-2016, 01:26

Only mappers made with LSI or with CPLD/FPGA can have that kind of property. So most have 74LS670 and will need to be software initialized before the computer finishes booting for them to be usable properly.

Por zPasi

Champion (499)

15-02-2016, 10:44

l_oliveira wrote:

Only mappers made with LSI or with CPLD/FPGA can have that kind of property. So most have 74LS670 and will need to be software initialized before the computer finishes booting for them to be usable properly.

It is possible to do that with discrete logic: you'd need at least an oscillator, a counter, and muxers. But probably no-one has bothered to do it like that.

And I think after cold boot 670 defaults to zero, so OUT 255,0 should not crash a computer. But only after cold boot, and that is not actually guaranteed even then.

Por l_oliveira

Hero (534)

15-02-2016, 13:46

Oscillator? Why?

A 74LS670 can be built with discrete flipflops like 7474s (which are programmable which state they "wake up from reset" through SET/CLEAR pins), coupled with a 74153 but that would be a massive circuit. Not even worth considering as an option.

Por zPasi

Champion (499)

15-02-2016, 14:32

l_oliveira wrote:

Oscillator? Why?

Oscillator would toggle /WR of the 670s, and increase or decrease the counter. Or, maybe we could use the MSX clock signal instead of an oscillator. When the counter reaches 4, it would trigger the muxes for normal operation (A0 and A1 pins).

Por l_oliveira

Hero (534)

15-02-2016, 14:41

What counter?

Are you thinking of DRAM? If so, the clock for the refresh counter is the refresh pin from the Z80 CPU.

Por zPasi

Champion (499)

15-02-2016, 16:02

l_oliveira wrote:

What counter?

Are you thinking of DRAM? If so, the clock for the refresh counter is the refresh pin from the Z80 CPU.

No. At boot, the counter would loop from 0 to 3. Its output would be connected to 670's write address lines, and the D-lines 0 and 1. So it would init the pages.

When the counter would reach 4, it should trigger some filpflop, which stops the counting, and switches the muxes so that 670s would be disconnected from the counter and connected to A0, A1 and D0 to D4.

In theory it should work

Por l_oliveira

Hero (534)

15-02-2016, 16:04

Ah, a state machine to init them. I get it now.

But really it's just as bad as replicating the register file chip with discrete flipflops haha.

Por zPasi

Champion (499)

15-02-2016, 16:46

l_oliveira wrote:

Ah, a state machine to init them. I get it now.

But really it's just as bad as replicating the register file chip with discrete flipflops haha.

It's almost as bad, I know

Por l_oliveira

Hero (534)

15-02-2016, 17:18

I have that VG8020 with 256KB mapper.

Because I needed to mod the BIOS for it to work properly at 60Hz, I also added code to initialize the mapper on boot.

Por blackmsx

Expert (77)

15-02-2016, 22:49

zPasi wrote:

The idea is to duplicate the page register with a second pair of 670s. That duplicate is used just for back annotation. Maybe not the smartest way to do it, but works. Note the /BUSDIR, if you're building this as internal that line doesn't exist and is not needed.

I haven't tested this one, but I think it should work

(Ignore that transparent "hat" in the picture, I didn't notice I was saving with alpha)

Thanks!