wait 15 T-States between reading and writing to Vram

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By Bengalack

Hero (578)

Bengalack's picture

02-02-2022, 21:15

Grauw wrote:

Great work, can you create an openMSX ticket for this on GitHub as well?

Thanks for the follow-up. I've made one, here: https://github.com/openMSX/openMSX/issues/1402

Grauw wrote:

If you change the out (VDPIO),a to out (c),a, giving it two extra cycles, does the problem disappear? Just to give a ballpark idea of how big the timing error is.

Tried that, but it did not fix things on the real machine (tried the a1-wsx only this time).

Grauw wrote:

As a confirmation, in the openMSX debugger I hacked in a change where the border colour is set to red during the I/O, and to blue otherwise, and indeed it happens neatly after the blanking starts. (Could be a nice addition to the test.)

I added that in the test. Made an "iffytim2" .c/com-file with this visual aid.

Hopefully someone can make something out of it. Maybe there is something in all that vram-timings-material we have overlooked?

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