VDP rd/wr timing

Supporter (8)

07-07-2022, 12:10

I have a Sony F700 with a video problem. I have a problem with my Sony F700D. He occasionally repeats the previous character. I saw in my philips 8235 that the wait line of the Z80 is often activated. with the Sony that does not happen (anymore). Is there anyone who can tell if the wait in the sony should be activated and when. I'm afraid my MSX engine is broken. My memory doesn't suffer because it has been replaced by fast static memory

By PingPong

Enlighted (4175)

07-07-2022, 20:32

It is a v9938 VDP.
this vdp do not have a wait line to z80 so it is probably the msx engine that controls the wait

I do not assume that when you type you can overrun the VDP.
not sure, but i think the wait should only be asserted on M1 cycle....

By bert_hoogenboom

Supporter (8)

07-07-2022, 21:51

For one its not my tpyping thats the problem it repeats letter when the computer is displaying them ( bottom line of basic)
and yes the engine controls the wait line. my question is does it also puls wait low when doing IO to the VDP and when more. my engine does not controls the wait any more. iff i want to overwrite the engine i need to know when. Every I/O and mem access or just mem or just some of the I/O adresses??? I can program every adress in a ELPD or CLPD. i just need to know what adress and funtions.

By bert_hoogenboom

Supporter (8)

07-07-2022, 22:03

I have now a 2 clock cylce wait on I/O and now my display works perfect. but its now on every I/O port and i don't like that is also on I/O the sound and time and keyboard and cassette data timing. I like to know what is normal in the engine. A trace of a logic analyser with IORQ, MREQ, RD, WR, VDP_CSR, VDP_CSW and WAIT would be the best.

By Pentarou

Hero (580)

07-07-2022, 22:30

Have you tried the X7 input on the S1985? Adds 1 WS to VDP R/W if held low @ reset.

By PingPong

Enlighted (4175)

07-07-2022, 22:34

I'm not aware of WAIT line assertions on I/O even on VDP unless on MSX machines with clock higher than the std 3.58Mhz.
the MSX BIOS is far from too fast even for the vdp. Just a question. does the problem arise even on screen 1?
I ask because the MSX2 VDP is rougly two times faster than the TMS VDP in all screen modes except for the Screen 0 (40/80 column text mode) where it does require more wait than the old TMS.

By PingPong

Enlighted (4175)

07-07-2022, 22:42

Plus another question... Is the M1 wait cycle on old DRAM , also there?
If there is no M1 wait state the z80 is faster, you did not notice problems because of static ram but ALL z80 instructions are faster.... even the VDP I/O,
some out instructions take 1 to 2 t-states less if the M1 wait is not asserted. this does indirectly influence the timespan between , for example two consecutive out instructions to vdp, leaving the latter less time to do its work

By bert_hoogenboom

Supporter (8)

07-07-2022, 22:58

The problem i see for now is only screen 0 (DOS). I did not test any other screen yet. But i don't see any wait coming from the S1985. Even if i pul X7 low i don't see any wait from the S1985. I think i (or the previus owner, most likly me) broke that output somehow. So i want to create my own wait circuit outside the S1985. I also want to extend my RAM bank switch to 7 or 8 bits. at his moment the S1985 puls D5, D6 and D7 low when reading address 3C to 3F. now i have 4MB ram but its not using more than 512Kb. I need to make a pcb for that any way and i can put de wait circuit on there at the same time.

By Pentarou

Hero (580)

07-07-2022, 23:09

So, if the /Wait line is damaged and PingPong is correct, the problem is the missing WS during M1 and the VDP junk is just an unfortunate consequence?
There are a few circuits you can copy for the WAIT, for example look at the Omega MSX or Expert schematics.
There are also a few Mapper circuits, just use the (Google) search for them.

@PingPong: You have time to edit and add content to a message, please don't create a new message each time.

By bert_hoogenboom

Supporter (8)

07-07-2022, 23:45

Sorry i was not aware i was making a new comment every time.
I am just trying to find out if the waitcycle is on every I/O and memory cycle or just memory or just some I/O addresses. i have build a 2 clockcycle delay on de VDP and its looks good now.
Is just a wait om M1 and not if you you have a 2,3 or 4 byte instruction on read of byte 2, 3 or 4. and also on M1 in the interrupt acknowledge.
I need the correct timing to test my new SCSI hard and software. so that i can use my old SCSI drives again.

By Grauw

Ascended (10860)

08-07-2022, 02:33

M1 wait circuit is described in Zilog’s Z80 manual, figure 21 on page 24.