R800 has registers for interrupts, DMA, and memory mapper. Register bit assignments are shown below. The internal IO registers are accessed by bringing the /CSREG pin low. When the address signal A0 is “Low”, the pointer of the internal IO register is latched, and when it is “High”, the data is written. The pointer is auto-incremented at each data write, so high-speed data transfer to the memory mapper registers etc. is possible.
Unfortunately looking at the turboR schematics, it seems /CSREG (Chip Select of IO Address / Data Register) is hardwired to 5V (H), so the internal extension register can’t be accessed…
The details on the instruction pipelining are also interesting.
Note I put the translation I posted on the previous page on the MSX Assembly Page, where I will maintain it from now on. It also includes the translated pipelining figure.
Japanese MSX user Kinnoji managed to unearth a copy of the R800 User’s Manual and posted a few photos
That's fantastic, Grauw! Let's hope he scans and share the entire document as you requested, even if he said that it's not usual for Japanese people to do this kind of thing.
Note that although it’s included in Kinnoji’s tweet, this R800 schematic picture comes from the Panasonic FS-A1GT service manual, not the R800 user’s manual.
ARTRAG wrote:
What is MA13-MA23 ?
One of the pictures in Kinnoji’s second tweet gives the English description of these pin names (incomplete but these are amongst them). The turboR service manuals have the Japanese names.
In English: Mapper Address Bus. Japanese: DRAM Address Bus.
Page size seems to be 8K. How the R800’s internal mapper works exactly I don’t know (the description wasn’t among the pages Kinnoji shared), but I think if you read the Z280 and 80286 manuals it should give some general idea.
The mapper registers are not accessible on the turboR. However they are used as inputs when the Z80 in the T9769C is active and the R800 operates in slave mode, to give full external access to the entire DRAM. This is probably why the service manual refers to it differently, and has no mention of mapper.
ARTRAG wrote:
And DA0-DA10?
Those are DRAM Multiplexed Address Bus, for the direct CPU <-> DRAM interface. Since there are 11 pins, the maximum capacity is 4 MB?
