Any Interest in Homebrew MSX Hardware Club ?

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Por maxis

Champion (512)

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14-08-2015, 02:08

kanima wrote:

Yes, running smart would already increase the effective speed a lot, but unless somebody has already implemented all those smart features in an FPGA Z80 core, it is probably a lot easier to just increase the clock speed?

Maybe, since T80 goal was to emulate as close as possible the existing Z80 timing model.
IMHO, both approaches will require quite a significant development time. Simply the modern memories don't use 8 bit data buses any more. So, at least implementing the 16/32 bit instruction prefetch, early decoding will already reduce the memory bandwidth constraint. So, the system will run much faster at the same clock.

Por RetroTechie

Paragon (1563)

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15-08-2015, 15:18

kanima wrote:

running smart would already increase the effective speed a lot, but unless somebody has already implemented all those smart features in an FPGA Z80 core (..)

Done: NextZ80

But even without that: a Z80 spends a lot of clock cycles on 'internal stuff', during which memory isn't touched. And then there is:
* the M1 wait in MSX, which could go.
* the DRAM refresh cycles that follow each opcode fetch, which could be done in bursts (like in Turbo-R), or dropped if static RAM is used.
* I/O cycles, which in an FPGA Z80 core could be moved to a separate 'bus'.

So even on an 8-bit memory bus, a big speed-up is possible if you 'take the air out' between memory read/writes. More if you decrease the clocks-per-instruction for those opcodes where memory bandwidth isn't a bottleneck.

And a clock speed bump, of course... :)

Por maxis

Champion (512)

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16-08-2015, 01:46

RetroTechie wrote:

Done: NextZ80

Well, no pipelining at all. Therefore - limited max speed. BTW, this is typical for the first generation RISC processors B-)
Good step forward, however. This core is slightly faster than boosted 3x Z80.
Still, IMHO, 16 bit instruction/data bus will increase dramatically subroutine calls rate, etc when word aligned.

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